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active bank will begin to precharge on the rising edge which is CAS Latency (CL) clock cycles before
the end of the read burst.
Auto-precharge is also implemented during Write commands. The precharge operation engaged by
the Auto-precharge command will not begin until the last data of the burst write sequence is properly
stored in the memory array.
This feature allows the precharge operation to be partially or completely hidden during burst read
cycles (dependent upon CAS Latency) thus improving system performance for random data access.
The RAS lockout circuit internally delays the Precharge operation until the array restore operation
has been completed (t RAS satisfied) so that the Auto-precharge command may be issued with any
read or write command.
8.7.1
Burst read with Auto-precharge
If A10 is HIGH when a Read Command is issued, the Read with Auto-precharge function is engaged.
The DDR2 SDRAM starts an Auto-precharge operation on the rising edge which is (AL + BL/2) cycles
later from the Read with AP command if t RAS (min) and t RTP (min) are satisfied. (Example timing
waveform refer to 11.22 Burst read operation with Auto-precharge diagram in Chapter 11)
If t RAS (min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until
t RAS (min) is satisfied.
If t RTP (min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until
t RTP (min) is satisfied.
In case the internal precharge is pushed out by t RTP , t RP starts at the point where t RTP ends (not at the
next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-
precharge to the next Activate command becomes AL + RU{ (t RTP + t RP ) / t CK(avg) } (Example timing
waveform refer to 11.23 Burst read operation with Auto-precharge diagram in Chapter 11.) , for BL = 8
the time from Read with Auto-precharge to the next Activate command is AL + 2 + RU{ (t RTP + t RP ) /
t CK(avg) }, where RU stands for “rounded up to the next integer”. In any event internal precharge does
not start earlier than two clocks after the last 4-bit prefetch.
A new bank active command may be issued to the same bank if the following two conditions are
satisfied simultaneously.
?
?
The RAS precharge time (t RP ) has been satisfied from the clock at which the Auto-precharge
begins.
The RAS cycle time (t RC ) from the previous bank activation has been satisfied.
(Example timing waveforms refer to 11.24 to 11.25 Burst read with Auto-precharge followed by an
activation to the same bank (t RC Limit) and (t RP Limit) diagram in Chapter 11)
8.7.2
Burst write with Auto-precharge
If A10 is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged.
The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write
plus write recovery time (WR) programmed in the mode register. The bank undergoing Auto-
precharge from the completion of the write burst may be reactivated if the following two conditions are
satisfied.
?
?
The data-in to bank activate delay time (WR + t RP ) has been satisfied.
The RAS cycle time (t RC ) from the previous bank activation has been satisfied.
(Example timing waveforms refer to 11.26 to 11.27 Burst write with Auto-precharge (t RC Limit) and
(WR + t RP Limit) diagram in Chapter 11)
Publication Release Date: Sep. 24, 2013
- 28 -
Revision A09
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